1. Field of the Invention
The present invention generally relates to integrated circuits and more particularly to an improved method and structure which reduces the size of semiconductor devices.
2. Description of the Related Art
Integrated circuit devices are continually being made smaller in order to increase speed, make the device more portable and to reduce the cost of manufacturing the device. However, certain designs have a minimum feature size which cannot be reduced without compromising the integrity of electrical isolation between devices and consistent operation of the device.
For example, dynamic random access memory devices (DRAMs) which use planar metal oxide semiconductor field effect transistors (MOSFETs) with deep trench (DT) storage capacitors have a minimum features size of approximately 0.15 .mu.m. Below that size, the internal electric fields exceed the upper limit for storage node leakage which decreases retention time below an acceptable level. Therefore, there is a need for different methods and/or different structures to further reduce the size of integrated circuit devices.